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Mar 10, 2012


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Girish Karanam

Thanks for the nice article.
Is there a difference between IO pads for flipchips and wirebond?


Alan Sguigna

Thank you Girish.
Could you elaborate on the context of your question: are you really asking if there is a difference in the PHY margin (eye diagram) if the die is wire-bonded versus placed in a flip-chip carrier? Or are you addressing the physical differences in the connection between the two?

Girish Karanam

My question about the IO design itself. I mean, can we use one IO for both flip-chip and wire-bond? or the IOs are separately/specially designed for flip-chip & wire-bond.


Alan Sguigna


In general, chip designers strive to make “one die” with “one PHY” during logical design and to submit that one logical design for packaging. There is a fundamental difference in making a die for a wire-bond (bond pads around the periphery) and making a die for a flip-chip (bumps distributed across the die) -- the change happens during the last phase of design, physical layout. There aren’t too many companies that make die for both - they usually make die for one or the other (only go through physical layout once).

The worst case design is the wire-bond — largest pads, most environmental issues (capacitance, resistance, etc.), and most uncertainty since the bond wires can touch or bend or be non-uniform in shape, etc. If the chip is logically designed for the wire-bond and includes enough tuning space to accommodate the possible changes and challenges of the wire-bond package, then it has more than enough adjustment and margin for a flip-chip design. So, if a company actually designs a chip for both, then they will most likely design it to the drive-specification and give it the tuning margin to handle the wire-bond — and will then submit it to different physical layout processes to end up with two different die masks that result in two different die types coming out of the fab. The different die then go to different packaging processes.

In summary, if a die is designed for wire-bond, it can be reused for flip-chip. However, if a design is made specifically for the higher-performance flip-chip (optimized to have smaller PHY drive, smaller bumps, shorter connections, etc.), then it most likely cannot be reused for wire-bond, without going through logic re-design and different physical layout.

Hope that helps.



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