In the article DDR4 Memory Timing Margining, we described more sophisticated DDR margining tests, which determine crosstalk coupling between aggressor channels, dwords (lanes 0-31), words, bytes and lanes. How can designers use these capabilities?
Sophisticated DDR margining tests measure the effects of crosstalk within the DDR interface. These tests determines which aggressor lanes, or groups of lanes, have the most impact on a given target signal, or “victim” lane. Using this information a platform developer can assess whether there is any unexpected coupling and take actions to understand and mitigate it as appropriate.
These powerful tests generate lane-to-lane crosstalk metrics and signal group (channel or byte group) to lane crosstalk metrics. For example, they can evaluate the effect of lane 22 on lane 32 within channel 0 or the effect of all of the channel 1 signals as a group on lane 32 in channel 0. They can be configured to provide a complete lane-by-lane profile of a system or a quicker byte group assessment. And, they can perform both timing and voltage margining tests, for both DDR3 and DDR4, as per the following:
- Read cycle timing offset
- Write cycle timing offset
- Internal Vref offset (default)
- DIMM Vref
For crosstalk coupling tests, two impact metrics are reported:
- A score metric - a normalized value of the impact for each aggressor or aggressor group upon the validation lane.
The crosstalk effects are evaluated by measuring the error rate using a baseline pattern for a given validation lane and then manipulating this pattern to isolate the effects of the aggressors, noting how the error rate associated with the validation lane is affected. The more the error rate changes, the more influence the manipulated lane(s) has on the validation lane. This error rate is converted to a normalized number relative to the error rate produced by the baseline pattern.
- A margin impact metric - a measure of how many margin steps an aggressor has on the validation lane.
The margin impact metric is determined by measuring the margin step difference between the margin step where the baseline error was measured and the margin step where the manipulated pattern produces the same error rate.
Test results are shown in both graphically and in raw numerical form. These help to show the lane-to-lane crosstalk both visually and in numerical form for later, deeper analysis. Test results can be merged from multiple test runs; for example, one can merge results from multiple margin parameters or directions. If time allows, it is possible to test multiple margin parameters and directions to increase the quality of the results.
An example below shows the results for testing an entire channel as the aggressor to a single bit. The chnl, dword, word and byte columns can be used to identify the aggressor. In the case of a channel aggressor the dword, word, and byte will have the value ‘all’:
The victim lane is 0 from channel 1, and it can be seen that the norm_score is 99, suggesting a high coupling.
The tool continues testing smaller combinations of lanes (aggressor dword vs. validation lane, aggressor word vs. validation lane, etc). Each aggressor has two rows in the example below. In the first two rows dword 0 (lanes 0-31) are tested as aggressors, followed by word 0 (lanes 0-16), and then byte 0:
Finally, each lane is tested individually as an aggressor against the validation lane. Most lanes show a varying degree of impact, but lanes 2 and 6 stand out. Both have low scores (8 and 19 respectively) and the margin impact is reported at 0. Further, lanes 1 and lane 4 have the maximum scores of 99 and high margin impact metrics:
As per-line transfer rates continue to climb, and voltages drop, design and manufacturing defects and variances have a greater effect on the signal integrity, performance and reliability of today’s designs. For more information on these correlations, a couple of good references are Board Test of DDR3/DDR4 Memory and Serial I/O, and System Marginality Validation of DDR Memory and Serial I/O.