Last month, we saw how defects on memory data lines can cause a system to fail, and yet escape detection by the system boot loader or BIOS. Let’s examine this in more technical detail.
Last month, we saw how defects on memory data lines can cause a system to fail, and yet escape detection by the system boot loader or BIOS. Let’s examine this in more technical detail.
Posted by Alan Sguigna on May 19, 2013 in Embedded Diagnostics, High-Speed I/O, Intel® IBIST, Non-intrusive Board Test (NBT), Processor-Controlled Test (PCT) | Permalink | Comments (0)
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Think about it. Test without touching a single bus with probles. Test without expensive fixtures. Soft access through existing board connectors and JTAG ports to create virtual, re-programmable test points. Wherever you want them. Whenever you want them. Clearly, 'mechanical test' is the way of the past and a software-driven approach is the future. But it's here and now.
This is non-intrusive board test, or NBT, becuase it really does not contaminate your tests results in any physical way. And that is important as speed continues to increase and physical access goes away. Instead, non-intrusive test relies solely on a combination of embedded instrumentation, onboard test structures and tools that access the test object through software or 'soft access'.
Learn all about non-intrusive board test directly from Adam Ley, Chief Technologist at ASSET InterTech, provider of the soft access ScanWorks platform for board debug, validation and test, by registering for our eBook, "Defect Coverage | Non-intrusive Board Test eBook".
Posted by Johan Renberg on Apr 30, 2013 in Boundary Scan, High-Speed I/O, Non-intrusive Board Test (NBT), Processor-Controlled Test (PCT) | Permalink | Comments (1)
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In the first two parts of this multi-part blog, we reviewed different kinds of short circuit, open circuit, and stuck-at faults and how they might affect link performance. Let’s recap and rank these defects and see what we can do about them.
Continue reading "Structural Defects on High-Speed Serial I/O - Part 3" »
Posted by Alan Sguigna on Mar 31, 2013 in Boundary Scan, High-Speed I/O, Intel® IBIST, Processor-Controlled Test (PCT) | Permalink | Comments (0)
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It’s all about time management in product development. Nowhere is time management more critical than during board bring-up, when the bare metal software needs to be integrated with the new hardware platform. The problem is a chicken-or-egg issue. You need the hardware to develop the software. To have functioning hardware, you need some bare-metal software. What happens then?
Posted by Larry Osborn on Dec 11, 2012 in Non-intrusive Board Test (NBT), Processor-Controlled Test (PCT) | Permalink | Comments (0)
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In my last few blogs, I’ve talked about the challenges of testing QPI, PCI Express, SATA 3, and DDR3 memory. These buses are common to many Intel Sandy Bridge and Ivy Bridge motherboard designs. Should test engineers take chances and just not test them?
Continue reading "Testing Intel Sandy Bridge and Ivy Bridge" »
Posted by Alan Sguigna on Sep 30, 2012 in Boundary Scan, High-Speed I/O, Intel® IBIST, Non-intrusive Board Test (NBT), Processor-Controlled Test (PCT) | Permalink | Comments (0)
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Today’s digital devices are ever so configurable. In days past, a device with 100-200 registers to configure in a design was considered large. By today’s standards, this is tiny. Many technical reference manuals on a single device exceed 3,000 pages and many of these pages are devoted to the configurability of the part. Chapter upon chapter in these massive tomes describe every possible bit and every conceivable configuration option.
Continue reading "Be an expert where it matters most to your customer" »
Posted by Larry Osborn on Aug 30, 2012 in Non-intrusive Board Test (NBT), Processor-Controlled Test (PCT) | Permalink | Comments (0)
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Last week I published a blog on detecting defects on PCI Express. Does Intel QuickPath Interconnect (QPI) differ in any way?
Posted by Alan Sguigna on Aug 26, 2012 in Boundary Scan, High-Speed I/O, Intel® IBIST, Non-intrusive Board Test (NBT), Processor-Controlled Test (PCT) | Permalink | Comments (0)
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PCI Express (PCIe) buses, in particularly Gen3, are susceptible to defects which may be masked from conventional test. What are these defects and how are they detected?
Posted by Alan Sguigna on Aug 16, 2012 in Boundary Scan, High-Speed I/O, Industry Standards and Forums, Intel® IBIST, Non-intrusive Board Test (NBT), Processor-Controlled Test (PCT) | Permalink | Comments (0)
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Ever have a PC die after a couple weeks or just after the warranty expires? Or perhaps the PC never powered up! Or maybe you have features like USB, a display or camera on the PC that don’t work. So you attempt to return it to the store where you purchased it only to find that it has to go back to the manufacturer. Ever wonder where those motherboards or laptop returns go? Or do you wonder how or why the faulty product ever shipped in the first place?
Posted by Larry Osborn on Aug 13, 2012 in Non-intrusive Board Test (NBT), Processor-Controlled Test (PCT) | Permalink | Comments (0)
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Recent surveys by iNEMI (International Electronics Manufacturing Initiative) validated what many engineers have experienced firsthand. Testing high-speed memories soldered to a circuit board is as elusive as it is critical for overall system performance. Testing DDR3 and DDR4 memory buses can be particularly tricky, given the fact that DDR is so fast and that the bus carries the clock and data on both the rising and falling edges of the signal. Sorting all of that out and making sure it stays sorted out over the life cycle of a system can be a daunting challenge.
Posted by Alan Sguigna on Jul 25, 2012 in Boundary Scan, High-Speed I/O, IJTAG, Non-intrusive Board Test (NBT), Processor-Controlled Test (PCT) | Permalink | Comments (0)
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