Test Data Out (TDO)

The Coming Crisis in Board Bring-Up

I was reflecting on how much processor speeds, memory, and data transmission rates have increased over the last few decades. And yet the same old tools and techniques are often used to bring up new designs. When do you think we fall off the cliff?

Programming devices at In-Circuit Test?

I read a very interesting article recently making the case for programming PLDs and Flash Memory at In-Circuit Test (ICT). What do you think?

PCT Detects Link Training Failures

One of our customers was experiencing field returns when 10 Gigabit Ethernet ports started failing to pass traffic at full line rate. How could they test for these failing boards in manufacturing and prevent them from getting out to customers?

Board Bring-Up

Board bring up of an early prototype is one of the most important steps for a design team. The first boards must pass through a battery of tests to demonstrate that the hardware is rock-solid. Non-intrusive technologies can be used to accelerate this process.

More Problems with In-Circuit Test

I found an interesting article on the pros and cons of ICT recently at http://www.electroviews.com/test/in-circuit.php. The document is a little dated (it looks like it was written in 2007), so I thought I would capture the essence of what was listed in this paper and add in some comments as well:

The Limitations of ICT

Is that old bed-of-nails rather prickly these days?

Legacy In-Circuit Test (ICT) has been diminishing in value for a long time. Let’s explore some of the current technical issues with ICT as test access on new circuit board designs continues to disappear.

The test stack

Those of you with a telecom background are no doubt aware of the “OSI Network Model”, also known as the OSI pyramid or stack. It is a way of sub-dividing a communications system into smaller parts called layers. A layer is a collection of similar functions that provide services to the layer above it and receives services from the layer below it. A decade ago, the telecommunications test industry underwent a revolution when platforms emerged that could cover multiple layers of the OSI stack. Now, the same thing is happening in the circuit board test industry...

Testing 2nd generation Intel® Core™ microarchitecture (aka Sandy Bridge)

Some of you may have noticed Intel’s announcement this past week at CES of the new generation of desktop/mobile processors, the 2nd Generation Intel® Core™ family. These processors are based upon a new microarchitecture at a 32nm process node. This increased level of density and functionality requires new board testing strategies...

Test coverage using multiple technologies

It is a well-known fact that manufacturing test strategies must involve a combination of inspection, structural, and functional test technologies in order to yield highest quality and minimize customer returns. But a new breed of non-intrusive, software-based technologies promises to disrupt legacy test solutions by guaranteeing the highest test coverage at the lowest cost. These technologies leverage off of the embedded instruments within silicon to achieve this goal in the following ways...

Intel® Xeon® Processor 7500 Series (codenamed Nehalem-EX)

The new Intel® Xeon® Processor 7500 Series (codenamed Nehalem-EX) is truly a leap forward for Intel server technology and forms the foundation for high-end clusters and supercomputers for years to come. Capable of scaling up to 256 processors and supporting 16 terabytes of memory, it will be used in high-performance “super nodes” running bandwidth-demanding applications like financial analysis, numerical weather predictions and genome sequencing. In short, this Intel platform rocks. The diagram below shows the new architecture, which is explained in our free whitepaper...