Part 1 of a three-part blog
To date, 3D chips have been fabricated in a number of ways, including stacking packages, flip chips, bonded bare die and others. Their names also tend toward the exotic, like PoP (package-on-package), PiP (package-in-package) and SiP (system-in-package). Now, a new methodology has emerged involving directly stacking wafers or die and connecting them with through-silicon-vias (TSV).
The majority of today’s 3D chips with TSVs feature interposers and are correctly referred to as 2.5D chips. Soon though, true 3D chips with TSV will reach volume manufacturing because a great deal has been invested in R&D and many different formulations of test chips have been investigated. One problem that still remains is how to test true 3D chips with TSV. JTAG or IEEE 1149.1 boundary-scan as well as IEEE 1687 Internal JTAG (IJTAG) could provide the basis for a solution.