Test Data Out

Structural Defects on High-Speed Serial I/O - Part 2

In my previous blog, we reviewed the effects of a missing capacitor and a short to ground on the performance of high-speed serial buses. What other kinds of defects should be considered, and what can we do about them?

IEEE 1149.7 JTAG Tutorial | eBook

One of the most frequently downloaded resources on the ASSET web site is the tutorial on IEEE Std.1149.7, and with good reason.  This complementary superset of the original IEEE Std 1149.1 (JTAG) enhances functionality of the Test Access Port, extends acces to multiple cores on SOC or multiple die in SIP or POP, and paves the way for use of JTAG in applications where it may not have previously been considerd.

The author of the tutorial is Adam Ley, Chief Technologiest at ASSET InterTech.  Adam served as the chief author of the draft standard.  Retrieve the tutorial from http://www.asset-intertech.com/Products/IJTAG-Test/IJTAG-Test-Software/IEEE-1149-7-Embedded-Tutorial

                                                                                        

Adaptive Equalization and Power Consumption

Poorly tuned adaptive equalization will cause systems to gulp power, instead of sipping it. What’s the technology behind this?

Structural Defects on High-Speed Serial I/O

Shorts and open circuits on high-speed serdes buses, such as PCI Express, may have subtle and difficult-to-diagnose effects on system performance. In other words, you might not know about them until customers start complaining and you get warranty returns. What kind of effects are these, and how are they prevented?

Cache-as-RAM for board bring-up of non-booting circuit boards

My last blog was about eliminating throw away code during product debug. Often, the designer faces even more critical issues during circuit board bring-up. In fact, it’s something of a catch-22 where hardware requires bare metal software and bare metal software requires functioning hardware.

DDR4, Signal Integrity, and Power Integrity

One of the biggest design challenges today revolves around maintaining signal integrity in the presence of power and ground rail fluctuations due to simultaneously switching signals. This is particularly true for DDR4 memory.

Signal Integrity Margins of different DIMM Suppliers

Not all memories are created equal. Some DIMM suppliers’ cards have margins that are better than others. And of course, the better the margins, the better the performance of the system, and the fewer blue screens.

How to avoid poor serdes performance caused by circuit board manufacturing variances

Validating high-speed serdes transmission lines on prototype circuit boards will certainly give you a level of confidence in the design. The problem is that this confidence can quickly erode during volume manufacturing because of the variances inherent in manufacturing processes. If undetected, these variances can increase warranty returns and repair costs downstream. We’ve just written a new e-book that explores this problem and describes solutions.

IEEE P1687 Internal JTAG (IJTAG) taps into embedded instrumentation

There’s a wealth of test and measurement IP trapped inside chips and it’s ready for the IJTAG standard to set it free. When that happens, you’ll be able to validate, test and debug circuit boards and systems better. The IEEE P1687 Internal JTAG (IJTAG) working group has been toiling away for several years now, codifying an open industry standard for accessing, managing and automating the operation of embedded instruments. Recently, we published a white paper about IJTAG, “IEEE P1687 Internal JTAG (IJTAG) taps into embedded instrumentation.”

The Intel Cougar Point SATA Bug

In early 2011, Intel discovered a design issue on their Cougar Point chipset, and took an approximately $700 million charge against earnings to repair and replace affected parts and systems.  What may have been the root cause of this, and how may it have been prevented?