Test Data Out

SIV versus SMV – Part 2

Last week we saw a $300,000 oscilloscope. This week, we look at another one for $470,000. The sky’s the limit when it comes budgeting for ‘scopes. But aside from the price, what other advantages are there of embedded instrumentation-based system marginality validation tools?

Signal Integrity Validation (SIV) versus System Marginality Validation (SMV)

Back a few years ago, engineers used expensive high-end oscilloscopes to perform signal integrity validation (SIV) on their designs, and considered that adequate in determining the success of a design. But with today’s products, process and parameter variations occur that require system marginality validation (SMV) to be done by less expensive software-based tools, to determine if a design is ready for high volume production.

Structural Defects on High-Speed Serial I/O - Part 3

In the first two parts of this multi-part blog, we reviewed different kinds of short circuit, open circuit, and stuck-at faults and how they might affect link performance. Let’s recap and rank these defects and see what we can do about them.

Adaptive Equalization and Power Consumption

Poorly tuned adaptive equalization will cause systems to gulp power, instead of sipping it. What’s the technology behind this?

Structural Defects on High-Speed Serial I/O

Shorts and open circuits on high-speed serdes buses, such as PCI Express, may have subtle and difficult-to-diagnose effects on system performance. In other words, you might not know about them until customers start complaining and you get warranty returns. What kind of effects are these, and how are they prevented?

DDR4, Signal Integrity, and Power Integrity

One of the biggest design challenges today revolves around maintaining signal integrity in the presence of power and ground rail fluctuations due to simultaneously switching signals. This is particularly true for DDR4 memory.

Signal Integrity Margins of different DIMM Suppliers

Not all memories are created equal. Some DIMM suppliers’ cards have margins that are better than others. And of course, the better the margins, the better the performance of the system, and the fewer blue screens.

How to avoid poor serdes performance caused by circuit board manufacturing variances

Validating high-speed serdes transmission lines on prototype circuit boards will certainly give you a level of confidence in the design. The problem is that this confidence can quickly erode during volume manufacturing because of the variances inherent in manufacturing processes. If undetected, these variances can increase warranty returns and repair costs downstream. We’ve just written a new e-book that explores this problem and describes solutions.

The Intel Cougar Point SATA Bug

In early 2011, Intel discovered a design issue on their Cougar Point chipset, and took an approximately $700 million charge against earnings to repair and replace affected parts and systems.  What may have been the root cause of this, and how may it have been prevented?

Margins (Eye Diagrams) follow the Silicon – Part 2

In my previous blog I covered at a high level why system signal integrity is highly dependent upon the silicon. Let’s dive into this a little deeper by first looking at wafer and die manufacturing variances.