Test Data Out (TDO)

Overclockers Unite!

The new Sandy Bridge E (Enthusiast) processors are a gamer’s delight. With the new LGA2011 socket and X79 chipset, Intel Sandy Bridge-E series processors come with enhanced performance overclocking support. But is it worth the money?

Your laptop - are you getting what you paid for?

Many of us got new laptops, e-readers, tablets, and other electronics toys as gifts over the holidays. But do these machines run as fast as they’re supposed to?

The Coming Crisis in Board Bring-Up

I was reflecting on how much processor speeds, memory, and data transmission rates have increased over the last few decades. And yet the same old tools and techniques are often used to bring up new designs. When do you think we fall off the cliff?

Solving Intel QuickPath Interconnect and DDR Margining Issues

This past week ASSET and Intel did a presentation at the Intel Developers Forum (IDF) on using ScanWorks to solve QPI and DDR3 margining problems.

Board Bring-Up

Board bring up of an early prototype is one of the most important steps for a design team. The first boards must pass through a battery of tests to demonstrate that the hardware is rock-solid. Non-intrusive technologies can be used to accelerate this process.

The Experts weigh in on Serial-Data Link Testing

Today I read an interesting article in Electronic Design magazine about the complexity of testing third-generation serial-data technology. With comments from Agilent, Tektronix and LeCroy, the article highlights all of the problems associated with oscilloscopes, BERTs, AWGs and other “heavy-metal” products, and not surprisingly doesn’t say anything about the elegant alternative of using embedded instrumentation…

The Limitations of ICT

Is that old bed-of-nails rather prickly these days?

Legacy In-Circuit Test (ICT) has been diminishing in value for a long time. Let’s explore some of the current technical issues with ICT as test access on new circuit board designs continues to disappear.

The test stack

Those of you with a telecom background are no doubt aware of the “OSI Network Model”, also known as the OSI pyramid or stack. It is a way of sub-dividing a communications system into smaller parts called layers. A layer is a collection of similar functions that provide services to the layer above it and receives services from the layer below it. A decade ago, the telecommunications test industry underwent a revolution when platforms emerged that could cover multiple layers of the OSI stack. Now, the same thing is happening in the circuit board test industry...

Test coverage using multiple technologies

It is a well-known fact that manufacturing test strategies must involve a combination of inspection, structural, and functional test technologies in order to yield highest quality and minimize customer returns. But a new breed of non-intrusive, software-based technologies promises to disrupt legacy test solutions by guaranteeing the highest test coverage at the lowest cost. These technologies leverage off of the embedded instruments within silicon to achieve this goal in the following ways...

Hope is not a strategy…

The world of validation has changed dramatically over the last few years due to the added challenge of increasing bus speeds. My observation across the industry is there are two camps companies are aligning on. In one camp, validation has changed significantly due to the bus speeds and board access challenges. In the other camp, validation is considered too costly due to the signal integrity (SI) challenges and is either minimized or eliminated...