Test Data Out

Defect Coverage | Non-intrusive Board Test eBook

Think about it. Test without touching a single bus with probles. Test without expensive fixtures. Soft access through existing board connectors and JTAG ports to create virtual, re-programmable test points. Wherever you want them. Whenever you want them. Clearly, 'mechanical test' is the way of the past and a software-driven approach is the future. But it's here and now. 

This is non-intrusive board test, or NBT, becuase it really does not contaminate your tests results in any physical way. And that is important as speed continues to increase and physical access goes away. Instead, non-intrusive test relies solely on a combination of embedded instrumentation, onboard test structures and tools that access the test object through software or 'soft access'.

Learn all about non-intrusive board test directly from Adam Ley, Chief Technologist at ASSET InterTech, provider of the soft access ScanWorks platform for board debug, validation and test, by registering for our eBook, "Defect Coverage | Non-intrusive Board Test eBook".

PXI meets embedded instrumentation

PXI is a hardware-based modular test standard. If PXI users want to add test capabilities, they have to add another hardware module to a PXI card cage. Now that’s changed with the new ScanWorks® PXI-1000 controller. Let’s say you have ScanWorks and a PXI-1000 controller and you’re doing boundary-scan test (IEEE 1149.1 and 1149.6), but you want to detect a broader spectrum of structural defects so you add another embedded instrumentation test technology like IJTAG (IEEE P1687 Internal JTAG). No, you won’t need another PXI-1000 controller. You just expand the capabilities of ScanWorks and the PXI-1000 that’s already in your PXI chassis takes care of the rest. PXI, meet embedded instrumentation.

Structural Defects on High-Speed Serial I/O - Part 3

In the first two parts of this multi-part blog, we reviewed different kinds of short circuit, open circuit, and stuck-at faults and how they might affect link performance. Let’s recap and rank these defects and see what we can do about them.

Testing Intel Sandy Bridge and Ivy Bridge

In my last few blogs, I’ve talked about the challenges of testing QPI, PCI Express, SATA 3, and DDR3 memory. These buses are common to many Intel Sandy Bridge and Ivy Bridge motherboard designs. Should test engineers take chances and just not test them?

Problems with Powered Opens on ICT

If you’re using Powered Opens on In-Circuit Test, you may not be getting the test coverage you expect.

Testing SATA 3

Serial ATA 3 (SATA 3, or SATA III) is a differential bus running at 6Gbps. It’s commonly used on computer motherboards, such as notebooks, to connect to mass storage devices. How do you know if your hard disk or flash drive is running at full speed?

Testing Intel QuickPath Interconnect

Last week I published a blog on detecting defects on PCI Express. Does Intel QuickPath Interconnect (QPI) differ in any way?

Testing PCI Express

PCI Express (PCIe) buses, in particularly Gen3, are susceptible to defects which may be masked from conventional test. What are these defects and how are they detected?

How to test DDR3, DDR4 and other memory buses is top-of-mind for many engineers. And rightfully so.

Recent surveys by iNEMI (International Electronics Manufacturing Initiative) validated what many engineers have experienced firsthand. Testing high-speed memories soldered to a circuit board is as elusive as it is critical for overall system performance. Testing DDR3 and DDR4 memory buses can be particularly tricky, given the fact that DDR is so fast and that the bus carries the clock and data on both the rising and falling edges of the signal. Sorting all of that out and making sure it stays sorted out over the life cycle of a system can be a daunting challenge.

You, our users, show us the full potential of new boundary-scan test tools

I’m always amazed how we learn from our users. Of course, whenever we add a new capability to the ScanWorks platform for embedded instruments, we believe we’ve done our homework, thoroughly researching the marketplace to identify the features needed by our users. So, for instance, we think that we know how a new JTAG test feature is going to be used. But over and over again, we end up learning from you the extent of a new feature’s full potential.