Test Data Out (TDO)

Why you need boundary scan in your board bring-up toolset

Did you ever need a new board coming off the production line yesterday and it wouldn’t boot? It didn’t even try to come up and gave you no hint why?  Typically you’d connect a debugger tool to see if you could get some signs of life. You might put some code into memory to start running some tests. But there’s no response from the processor and you can’t access any of the memory parts on the board. You’re stuck...

The Coming Crisis in Board Bring-Up

I was reflecting on how much processor speeds, memory, and data transmission rates have increased over the last few decades. And yet the same old tools and techniques are often used to bring up new designs. When do you think we fall off the cliff?

Don't be Intrusive!

Ever heard the old saw about the guy (gal) that “went to a fight and a hockey game broke out”?

I’d characterize the ongoing debate on the value and longevity of In-Circuit Test (ICT) as a bit of a brawl…

Board Bring-Up

Board bring up of an early prototype is one of the most important steps for a design team. The first boards must pass through a battery of tests to demonstrate that the hardware is rock-solid. Non-intrusive technologies can be used to accelerate this process.

What is JTAG? and What is IJTAG?

I’m sometimes asked how JTAG, IJTAG and boundary scan all relate to one another. Here’s a short explanation.

More Problems with In-Circuit Test

I found an interesting article on the pros and cons of ICT recently at http://www.electroviews.com/test/in-circuit.php. The document is a little dated (it looks like it was written in 2007), so I thought I would capture the essence of what was listed in this paper and add in some comments as well:

The Limitations of ICT

Is that old bed-of-nails rather prickly these days?

Legacy In-Circuit Test (ICT) has been diminishing in value for a long time. Let’s explore some of the current technical issues with ICT as test access on new circuit board designs continues to disappear.

The test stack

Those of you with a telecom background are no doubt aware of the “OSI Network Model”, also known as the OSI pyramid or stack. It is a way of sub-dividing a communications system into smaller parts called layers. A layer is a collection of similar functions that provide services to the layer above it and receives services from the layer below it. A decade ago, the telecommunications test industry underwent a revolution when platforms emerged that could cover multiple layers of the OSI stack. Now, the same thing is happening in the circuit board test industry...

Testing 2nd generation Intel® Core™ microarchitecture (aka Sandy Bridge)

Some of you may have noticed Intel’s announcement this past week at CES of the new generation of desktop/mobile processors, the 2nd Generation Intel® Core™ family. These processors are based upon a new microarchitecture at a 32nm process node. This increased level of density and functionality requires new board testing strategies...

Test coverage using multiple technologies

It is a well-known fact that manufacturing test strategies must involve a combination of inspection, structural, and functional test technologies in order to yield highest quality and minimize customer returns. But a new breed of non-intrusive, software-based technologies promises to disrupt legacy test solutions by guaranteeing the highest test coverage at the lowest cost. These technologies leverage off of the embedded instruments within silicon to achieve this goal in the following ways...