In Episode 2, I said we would be looking at the Multiplex IO (MIO) next, but before we dive into looking at the MIO, I have a desire, call it a nagging question, to look at the code in the QSPI. So I’ll divert this episode to that endeavor and return to the MIO initialization as soon I have an answer to my nagging question.
In Zedboard Video Chronicles Episode One, I powered up the Zedboard, loaded the Linux kernel and executed a couple of shell commands. Then, I connected to the JTAG interface and found that I had independent dual-core control of the Zynq 7020, as expected. Things were just about to get really interesting, but I ran out of time.
In this episode, I look at ways of conducting Zynq initialization, but only focus on the initialization of the DDR controller. My style of exploring silicon and development platforms is to start quickly in specific areas. By knowing what areas are often difficult to understand/control (gained via too many years of hard knocks in embedded software development), I take shortcuts often to maximize my learning in a brief period. Then later I go back and drill into the details, which can be tedious without having established a background beforehand.
I will cover the DDR initialization via macros, reverse-engineer said macros, explore where in the Xilinx tools to extract the data necessary for debugging, and explore where to find relevant data in the Technical Reference Manual quickly.
Check out the Zedboard Video Chronicles Episode Two
In our last episode, we left off just as we were beginning to configure the DDR via a SourcePoint Macro. In the Zedboard Chronicles Episode One, we stated that the code was running in OCM. How did we know that the cores were operating in the OCM?