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November 2016

Nov 06, 2016

Using Embedded Run-Control for PCIe Link Training Testing

It is often part of a hardware validation test suite to initiate multiple PCIe bus retrains, looking for hardware design issues, or LTSSM RTL bugs in the device under test. These test suites take a very long time to run. Is there a way to speed them up?

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Posted at 05:43 PM in Arium Probes | SourcePointâ„¢, Embedded Diagnostics, High-Speed I/O, Software Debug and Trace, Software Debug and Trace - ARM, Software Debug and Trace - Intel | Permalink | Comments (0)

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