Recently launched DDR4 devices have what memory device vendors may refer to as a “boundary scan” test mode. Even though there’s not really a boundary-scan function involved on the DDR4 side, this mode actually has been, as claimed by JEDEC, “designed to work seamlessly with any boundary-scan devices.” Here’s a brief introduction to what it does and how to test it with a boundary-scan (JTAG) tool.
Baseboard Management Controllers (BMCs) form the brains of any high-end Intel-based server platform: they perform system management functions ranging from fan speed control to remote user authentication. A new wave of these service processors is coming to market to support new capabilities needed on the next generation of Intel silicon. What are these unique features, and how will they be debugged?
As described in earlier blogs, the new Intel Innovation Engine (IE) makes an ideal host for validation, debug, trace and test applications on Intel platforms. This article details the implementation of a JTAG execution engine on the IE for the purposes of printed circuit board structural and functional testing.
Last week, I wrote about Intel’s public announcement of the Innovation Engine (IE), an Intel architecture processor and I/O sub-system embedded into their upcoming generations of server platforms. This article describes the use of the IE for JTAG boundary-scan testing of memories.