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Expanding PCOLA for 3D Die Stacks

Testing 3D chips | JTAG IJTAG and IEEE P1838 – Part 3 of a three-part series

The first and second blogs in this series discussed the PCOLA/SOQ/FAM test methodology for two-dimensional (2D) circuit boards and described how 3D stacked die devices are currently being tested. From a test perspective, 3D die stacks resemble circuit boards in many respects. This blog, the final in this three-part series, brings the discussion full circle by describing where the PCOLA methodology can help test 3D devices and where it needs to be supplemented.

How 3D stacks are being tested today

Testing 3D chips | JTAG IJTAG and IEEE P1838 – Part 2 of a three-part series

In Part 1 of this three-part blog series, I introduced various developments that have brought the industry to the current state of affairs with regards to 3D chip test. I also introduced the PCOLA board test methodology and explained that it could be applied to 3D chips. In addition, the work of the IEEE P1838 working group, which is developing a standard for 3D chip test, was discussed. So, where do we go from here? In this blog we’ll take a close look at the current state-of-the-art regarding 3D chip test. Specifically, we’ll look at how a high bandwidth memory (HBM) stack is tested.

Testing 3D chips | JTAG, IJTAG and IEEE P1838

Part 1 of a three-part blog

To date, 3D chips have been fabricated in a number of ways, including stacking packages, flip chips, bonded bare die and others. Their names also tend toward the exotic, like PoP (package-on-package), PiP (package-in-package) and SiP (system-in-package). Now, a new methodology has emerged involving directly stacking wafers or die and connecting them with through-silicon-vias (TSV).

The majority of today’s 3D chips with TSVs feature interposers and are correctly referred to as 2.5D chips. Soon though, true 3D chips with TSV will reach volume manufacturing because a great deal has been invested in R&D and many different formulations of test chips have been investigated. One problem that still remains is how to test true 3D chips with TSV. JTAG or IEEE 1149.1 boundary-scan as well as IEEE 1687 Internal JTAG (IJTAG) could provide the basis for a solution.