Testing 3D chips | JTAG IJTAG and IEEE P1838 – Part 3 of a three-part series
The first and second blogs in this series discussed the PCOLA/SOQ/FAM test methodology for two-dimensional (2D) circuit boards and described how 3D stacked die devices are currently being tested. From a test perspective, 3D die stacks resemble circuit boards in many respects. This blog, the final in this three-part series, brings the discussion full circle by describing where the PCOLA methodology can help test 3D devices and where it needs to be supplemented.