You may be familiar with the Intel® acronyms LBR (Last Branch Record), BTS (Branch Trace Store), and even AET (Architecture Event Trace). What other new debug and trace services are available on the latest Intel silicon?
There was a time when an at-speed functional test of anything required functional operating firmware. Not so for I2C serial interfaces anymore. A new test methodology involving IEEE 1149.1 JTAG (boundary scan), an FPGA and embedded instrumentation IP means that the design and manufacturing test teams don’t have to wait around for the software department to finish the firmware for a circuit board design. They can start testing right away. Even prototypes of the design. In addition, they don’t need to spend all that time developing functional test routines that won’t provide the kind of diagnostics that’s needed anyway.
The origins of JTAG are inextricably bound up with boundary scan. Yet, it provides many capabilities to many purposes. Often, as part of a point tool, whether for debug, programming, test or validation, it takes on just one capability. But, no matter the purpose, as the thread common to all, the standard Test Access Port (TAP) opens the way for many applications. In the test domain, several of these unite under the banner Non-intrusive Board Test (NBT).