In the article DDR4 Memory Timing Margining, we described more sophisticated DDR margining tests, which determine crosstalk coupling between aggressor channels, dwords (lanes 0-31), words, bytes and lanes. How can designers use these capabilities?
At their developers conference two weeks ago, PCI-SIG representatives talked about doubling the bandwidth of PCI Express 3.0, while still preserving channel runs of up to 20 inches, the length of the traditional server’s data path. How is this achieved?
Time-to-market can make or break many technology-based products today. Firmware development is often the task that drives completion schedule. If you need to shorten the time-to-market on your next project, would choosing the best tools for the job make a big difference?
Speeding up an electronics assembly line can significantly reduce costs for the manufacturer. In fact, a recent application note on in-line programming of SPI flash memory via JTAG and an FPGA showed programming times can be reduced from 22 minutes to 30 seconds. This saved the manufacturer more than $200,000 per year!
In a previous blog, we touched on some of the key attributes of Intel QuickPath Interconnect versus PCI Express Gen3, to explain why the acceptable bit error rate threshold of Intel QPI is two orders of magnitude lower. This article elaborates on how some of the key design features of QPI contribute to this more stringent requirement.
Serial ATA (SATA)-based systems come in a wide range of topologies and trace/cable lengths. This presents signal integrity challenges due to signal loss, reflection and crosstalk; causing SATA device detection problems, lack of interoperability, slower performance, and increased radio frequency interference. What are the main issues, and how do designers mitigate them?