The answer to these questions is an emphatic YES! Many silicon providers have included the P1687 architecture and are using both of the IJTAG languages, Instrument Connectivity Language (ICL) for describing the on-chip network and Procedure Description Language (PDL) for describing embedded instrument operations. So far, what’s been missing is public acknowledgement. It seems that many are waiting until the “P” for “preliminary” falls off the standard’s designation and the IEEE 1687 document is officially published before they “fess up” that they are, in fact, using it.
Be that as it may, a few early adopters have gone public and we, the IJTAG community, have managed to publish a paper or two. Most importantly, the imminent publication of the standard is leading to the emergence of an IJTAG ecosystem.
By IJTAG ecosystem we mean: 1.) Tools are needed to create and insert the IJTAG architecture and instruments into a chip design. This is usually the purview of an EDA company such as Synopsys, Mentor, Cadence or others. 2.) A silicon provider must require that the IJTAG architecture and associated instruments be embedded into a chip. 3.) A system development company must then incorporate the chip with the IJTAG instrument(s) and network onto a circuit board. 4.) A tool supplier, such as ASSET, must provide a tool that can take in a chip’s Boundary Scan Description Language (BSDL), ICL and PDL, and enable the operation of the embedded instruments in the silicon after the device has been placed on a circuit board. For a true ecosystem, all of the members must work together to make sure that information and files flow smoothly back and forth throughout the ecosystem. This effort is known as “interoperability”.
One such interoperability exercise was recently completed, first using an FPGA to prototype how the tools process would flow and then a second time when the contents of the prototype FPGA was incorporated into an ASIC for a real-world application. In this case, the embedded instrument was a scan compression circuit. The interaction of IJTAG tools required that ScanWorks operate the compression circuit and also extract data that could be coupled with a Synopsys gate diagnostic process to identify the source of a gate fault within the chip on the board (in-situ diagnostics to help eliminate the no-trouble-found issue). To find out more about the IJTAG “creation-insertion-to-operation-and-analysis” process, download our free eBook: “IEEE P1687 IJTAG Tools Ecosystem – A Case Study”.