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Apr 07, 2014


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Thanks, Alan, for keeping us informed, as always! Clearly, system margin validation (SMV), for obvious reasons, I suppose, continues to become more and more important as per-line transfer rates continue to climb.

Here are just a couple of comments by way of clarification - I hope they are of help!

• Regarding the circuit snip and the reference to the digital potentiometer - if the ISL90727 is used, for the stated purpose of margining the VREF, then the 1K resistors become NI (not installed) and the three (3) resistance terminals (RH, RW and RL) connect in their place (at the VDDQ, VREF and GND, respectively).

• Near the end, you say that, "But for DDR4, CMD/ADDR is becoming more of a margin limiter." To be clear, I believe that the referent for the "more" (than) here is CMD/ADDR for DDR3 (rather than, for example, DQ for DDR4 itself).

Alan Sguigna

My pleasure, Adam.

You are absolutely correct regarding the circuit snip.

And yes, both DQ and CMD/ADDR are margin limiters, but more attention must be paid to CMD/ADDR margining on DDR4. Design engineers usually focus on DQ voltage and timing margining as part of design validation, and ignore CMD/ADDR margining, but this is no longer practical for DDR4.

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