Determining the margins of a system requires taking a statistically large-enough data collection sample size to achieve a meaningful result. The sample size takes into account variances due to silicon process, temperature, voltage, finite test time, and a number of other factors. What is the math behind this?
Your board bring-up team is trying to verify the prototypes of a new product so it can move into manufacturing, but they’re stuck and it looks like the product’s going to be late to market. The team can’t perform its functional tests on the board’s serial interfaces like UART, SPI and I2C because the system’s functional software is not ready yet. It’s stuck in development.
Here’s are a few test methods that can un-stuck the board bring-up team. You can perform at-speed functional verification tests on the serial interfaces without – I repeat: without! – the system’s functional software.
With boundary-scan (JTAG) and an embedded instrument IP inserted into an on-board FPGA you don’t need the functional software to do your functional verification tests.
We know that the board bring-up process can be extremely challenging on today’s complex, high-speed designs. How do we get the iterative validation, test and debug steps off of the critical path of new product introduction?