Testing memories is often a real challenge, especially in large clusters soldered on to boards in production. A recent survey also shows this problem to be among the top 3 for test engineers.
Clearly, the ability to thoroughly test, characterize and diagnose faults and failures with soldered-down memory is one of the most pressing problems in the industry.
So, is there a solution when you have little or no physical access to memory? How are you going to validate memory that’s soldered on the board already? Using DDR3 memory as an example, this eBook discusses how boundary scan test and JTAG methods based on the IEEE 1149.1 standard can be used effectively by accessing memory through a memory management unit (MMU), microprocessor or FPGA.
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