In the first two parts of this multi-part blog, we reviewed different kinds of short circuit, open circuit, and stuck-at faults and how they might affect link performance. Let’s recap and rank these defects and see what we can do about them.
In my previous blog, we reviewed the effects of a missing capacitor and a short to ground on the performance of high-speed serial buses. What other kinds of defects should be considered, and what can we do about them?
One of the most frequently downloaded resources on the ASSET web site is the tutorial on IEEE Std.1149.7, and with good reason. This complementary superset of the original IEEE Std 1149.1 (JTAG) enhances functionality of the Test Access Port, extends acces to multiple cores on SOC or multiple die in SIP or POP, and paves the way for use of JTAG in applications where it may not have previously been considerd.
Shorts and open circuits on high-speed serdes buses, such as PCI Express, may have subtle and difficult-to-diagnose effects on system performance. In other words, you might not know about them until customers start complaining and you get warranty returns. What kind of effects are these, and how are they prevented?