In today’s market we have a choice of different types of flash memory devices – or, many of us might say, we have different devices that we can flash. We have NOR and NAND and then there is SPI. Each platform we adopt as a reference design to take advantage of some new hot processor also recommends what tool we should use for programming its flash. And, of course, it’s not a programmer in your arsenal of tools. So off you run to get Yet-Another-Programmer (YAP).
One of several buses I’ve been working on with the ScanWorks High-Speed I/O (HSIO) products is PCI Express (PCIe). We’ve had tools in ScanWorks to test PCIe in various ways since the Intel server chipset code named Twincastle back in the 2005 timeframe. And we’ve often run into issues with having robust enough support to handle any random endpoint that customers might choose for their system.
Isn’t it a great time to be a board designer? Compared to twelve years ago, the average number of nets has gone from 1,544 to 2,832; the number of pin-to-pin connections has increased from 7,661 to 13,573; the number of components has grown from 1,120 to 3,518; and many other challenges to the job have arisen.
