My neighbor’s son ripped out all the Cat 5e cable in his house and replaced it with Cat 6 cable. Why did he do that?
Yep, it was a long Saturday of crawling up into the attic, cutting through drywall, and cable-pulling. It’s harder with Cat 6 than Cat 5e because the former is thicker gauge, 22 AWG, versus 24 AWG. So the wire is heavier and doesn’t bend as well.
What was the point? Well, Cat 5e only goes up to 1000BASE-T/1000BASE-TX (Gigabit Ethernet). The boy wanted to have 10GBASE-T (10-Gigabit Ethernet, or 10GbE). I was told (although I haven’t verified this) that to run high-definition 1080P movies from his media server to any room in the house, you need to have something faster than Gigabit Ethernet. All I can say is, wow. And in the future, he wants to be able run 4K, the emerging digital television standard with 4,096 pixel horizontal resolution. Talk about future-proofing.
With people wanting to download 1080P today in the home, and 4K in the future, both server and networking technologies need to keep up. 40-Gigabit Ethernet (40GbE) and 100GbE are realities today. On a circuit board design, the XAUI physical interface for 1GbE is replaced by XLAUI and CAUI for 40GbE and 100GbE respectively. A great technical paper on these technologies can be found on the Ethernet Alliance’s website here. Both use 64b/66b encoding with a signaling rate of 10.3125 gigabaud per lane.
Not to be outdone, the PCI-SIG has announced PCI Express 4.0, with a rate of 16 GT/s per lane, double the throughput of the current PCIe Gen3. PCIe Gen4 is still a couple of years away from final specifications.
From my previous blog, you can see the design challenges with buses running at one-half these speeds: http://blog.asset-intertech.com/test_data_out/2012/03/high-speed-io-design-guidelines.html. The complexity of designing these products, and the simulation and measurement necessary to validate that they will perform as expected, will be formidable. For example, can you imagine how expensive an oscilloscope will be needed to validate PCIe Gen4? And how difficult it will be to get the testing done in the time available between board spins and volume manufacturing production? Migrating these test methodologies to a software-based approach using embedded instrumentation within chips is inevitable and necessary.