Test Data Out (TDO)

iNEMI Built-In Self-Test Project Wrap-Up

Last week iNEMI (the International Electronics Manufacturing Initiative) concluded its nine-month project investigating Built-In Self-Test (BIST). The purpose of the iNEMI Project was to develop and promote the adoption of chip BIST at the board and system level. ASSET staffers participated in the Project, as part of our embedded instrumentation initiative and our drive to standardize IC BIST using technologies such as IEEE P1687 (IJTAG). Here's a summary of the conclusions...

Why do I have to validate my board design?

For some of us this is a rhetorical question. Of course you will need to validate!! However, I’m surprised how much I am seeing this mindset in the marketplace.

ASSET has been providing validation tools for Intel Architecture (IA) based designs for the last six years. During this time, we have seen a significant increase in signal speeds that has created challenges to the signal integrity (SI) engineer. For example, moving to the Intel® QuickPath Interconnect (Intel QPI) bus changed the validation process. The maximum Intel QPI frequency on Nehalem is 3.2 GHz (6.4 GT/s). To put this in perspective, the maximum Front Side Bus frequency was 200 MHz. In one generation of IA based products, there was a 16x speed increase!

This increase in speed requires a new approach from designers. Read on...

QPI Is Cool...

Many of us are responsible for validating and testing Intel®-based designs. The latest Intel® Xeon® and Itanium® processor platforms use Intel’s QuickPath Interconnect (QPI) to tie the processor and the I/O hubs together into single, dual, and multi-processor systems. ASSET got a nice promotion in Intel’s book on QPI: “Weaving High Performance Multiprocessor Fabric: Architectural Insights into the Intel QuickPath Interconnect”.

For those who might be interested in the book, it’s available for about $80 from www.amazon.com. On pages 257-259, Intel talks about the ASSET ScanWorks® IBIST (Interconnect Built-In Self Test) tool. To quote:

Test Pads on High-Speed Nets

Recently I read a posting from a well-known In-circuit Test (ICT) vendor defending the use of test pads on high-speed signals. I found this message to be rather amusing, since the prevailing wisdom is to avoid these to prevent signal integrity issues.

The posting went something like this:

We have done some simulations that indicate that test pads can still be used for high speed signals if they are properly designed and added correctly to the PCB. The test pad must be on the signal etch without a stub connecting the etch to the pad. Also, there should not be a via connecting the etch to the test pad.

The results indicate that a 35 mil pad on a 5 mil wide etch is OK for 10Gb/s with 30ps rise/fall times.

If there is still a worry about test pads, the test pad can always be "compensated" by removing some of the reference plane below the test pad to diminish the additional capacitance that might otherwise occur. If the test pad per-unit capacitance and inductance is nearly equal to the per unit capacitance and inductance of the transmission line's etch, then the test pad will have no net negative effect to the signal transmission.

The first paragraph correctly highlights some of the pitfalls of putting test pads on high-speed signals. The trend these days is to route traces for high-speed signals on inner layers of the PCB – in which case it is only possible to add a test pad by way of a via, which is not a good idea.

Ever heard of PCOLA/SOQ/FAM ?

I’ve been in the test engineering industry for over a decade and the concept of test coverage has always been of great interest to me. How do test engineers quantify the amount of test coverage they get on a particular board design? We know from experience that every design is different and, therefore, every design needs a slightly different test strategy. That’s what makes our jobs as test engineers ever-changing and fresh. We’re always learning about new test strategies, technologies and methodologies and applying them to the task at hand. So as boards get bigger, denser, faster and more complex, we apply our creativity to keep test coverage apace with the changes.

Sometimes I wonder, is this science or black magic? I believe it’s both. One scientific innovation I’ve seen recently is the adoption of PCOLA/SOQ/FAM by iNEMI. Yeah, I know that’s a lot of letters strung together, but here’s what it means. iNEMI is the International Electronics Manufacturing Initiative and it is spearheading an industry effort to scientifically characterize test coverage. And that’s what PCOLA/SOQ/FAM is. Here’s what the alphabet soup means:

IEEE 1149.7 & 1687 - dispelling the misconceptions

Developing a new standard through the IEEE, JDEC or any other credible industry group is not a trivial undertaking, but the outcome typically generates widespread benefits for an entire industry. Sometimes, the tendency is to think that similar standards overlap in capabilities and that they can be deployed interchangeably. This misses the point – and the value – of new standards.

A recently minted standard, the IEEE 1149.7 enhanced boundary-scan standard, and the soon-to-be-ratified IEEE P1687 standard for embedded instruments offer significant value over the related IEEE 1149.1 boundary-scan standard and the IEEE 1500 standard for embedded core test.