Test Data Out (TDO)

Overclockers Unite!

The new Sandy Bridge E (Enthusiast) processors are a gamer’s delight. With the new LGA2011 socket and X79 chipset, Intel Sandy Bridge-E series processors come with enhanced performance overclocking support. But is it worth the money?

Performance versus Conformance Testing

OEMs in the telecom industry invest in verifying the performance and conformance of the high-speed interconnects off their gear. Does the same approach apply to chip-to-chip interconnects, and in other industries?

Don't be Intrusive!

Ever heard the old saw about the guy (gal) that “went to a fight and a hockey game broke out”?

I’d characterize the ongoing debate on the value and longevity of In-Circuit Test (ICT) as a bit of a brawl…

What is P1838 3D test?

Although it has been in the news for quite a while, one of the methods thought to be the way to extend Moore’s Law is finally reaching the point where it may be deployed in the near future — 3D Silicon Integration…

P1838: the 3D Standard and its use with 1687

One of the newest IEEE Standards Committees is currently defining the P1838 3D Test Standard. The main goal of P1838 is to develop a “Per Die” Access Mechanism that becomes a “Stacked Die” Access Mechanism when the individual die are stacked into 3D silicon. The main focus is to handle the configuration of stacking die that are connected to each other using Through-Silicon-Vias (TSV’s) to make 3D silicon integration, which is different from Package-on-Package and other 3D packaging techniques. Find out more…

What is JTAG? and What is IJTAG?

I’m sometimes asked how JTAG, IJTAG and boundary scan all relate to one another. Here’s a short explanation.

IEEE P1687 and In-Circuit Test (ICT)

I read an interesting paper recently suggesting that IEEE 1687-based tests were best run at ICT on the manufacturing floor. The article was, of course, written by an ICT vendor. This is patently not true and is even a little bit preposterous. Let me explain…

The test stack

Those of you with a telecom background are no doubt aware of the “OSI Network Model”, also known as the OSI pyramid or stack. It is a way of sub-dividing a communications system into smaller parts called layers. A layer is a collection of similar functions that provide services to the layer above it and receives services from the layer below it. A decade ago, the telecommunications test industry underwent a revolution when platforms emerged that could cover multiple layers of the OSI stack. Now, the same thing is happening in the circuit board test industry...

Test coverage using multiple technologies

It is a well-known fact that manufacturing test strategies must involve a combination of inspection, structural, and functional test technologies in order to yield highest quality and minimize customer returns. But a new breed of non-intrusive, software-based technologies promises to disrupt legacy test solutions by guaranteeing the highest test coverage at the lowest cost. These technologies leverage off of the embedded instruments within silicon to achieve this goal in the following ways...

Structural versus Functional Test, and Test Coverage versus Diagnostics

What’s the difference between circuit board structural test and functional test? And how does test coverage relate to diagnostics? These terms are sometimes used interchangeably, but not knowing the difference may result in a less-than-optimal test methodology. Let me explain…