The mission of the Open Compute Project (OCP) is to design and enable the delivery of the most efficient server, storage and data center hardware designs for scalable computing. ASSET has just joined the OCP to contribute to the reliability and availability of OCP designs.
Intel Processor Trace (Intel PT) is a capability on new Intel silicon that captures information about software execution using dedicated hardware facilities inside the chip. How is it used to debug UEFI?
Heterogeneous Computing refers to systems that use more than one kind of processor, typically a combination of CPUs and GPUs, sometimes on the same silicon die. Is this solution optimized for supercomputing applications?
Connectivity for hardware-assisted software debuggers on Intel® platforms is about to change radically. Over the years, debugging an Intel platform with a hardware-assisted debugger has been marked by a progression of printed circuit board (PCB) real estate-grabbing connectors. These connectors were designed to provide access to the processor for run-control and enable software debuggers.
Conventional printf statements within a BIOS being debugged add a lot of “backpressure” due to the overhead within the printf routine and the cost of directing the output through a slow serial port. This slows the debugging process down, and may even mask some time-sensitive bugs. Is there a better, more non-intrusive way?
In a previous blog, I described how the ScanWorks Embedded Diagnostics (SED) utility runs Intel CScripts nearly as fast as legacy methods. This applies in particular using the Emulex Pilot4 BMC, with its on-chip JTAG Master.