When the Extensible Firmware Interface (EFI) was being defined several years ago, debug resources were an important consideration. We all know that you can have great technology, but if you can’t effectively debug it, it’s not really all that great. Every new technology needs to be coupled with an efficient development paradigm for relatively easy adoption and deployment.
Since the early days of the PC, BIOS (Basic Input/Output System) was the firmware platform for booting a computer out of reset and for providing basic run-time services to an operating system. Of course, PCs have evolved over the years with new system architectures, processor technologies, option ROMs, security safeguards, addressing enhancements and many other innovations which meant that BIOS needed to expand as well. Over time, managing the assembly-level code of BIOS had become more and more problematic for the industry.
New silicon features, along with debugger tool features that use them, can make a large difference in the time it takes to find the really hard bugs encountered during each UEFI port. Intel® has recently introduced two very important debug features in its processors. These debug features are (1) Trace Hub, and (2) Intel Processor Trace. Source level debuggers like ASSET InterTech’s SourcePoint™ contain trace features that use these silicon debug hooks to offer some very strong tool elements that have never been found in the Intel environment before.
Silicon vendors like Intel have been saying for some time that pass/fail validation testing on high-speed I/O (HSIO) or serdes buses just doesn’t cut it anymore. Why? As the speed of HSIO buses has continued to increase, they’ve gotten much more sensitive and susceptible to signal integrity problems which can lead to failures or throughput degradations. A bus might pass a validation test in the development lab, but its operating margin relative to the eye mask might be very slight. And that’s not good.
Recently launched DDR4 devices have what memory device vendors may refer to as a “boundary scan” test mode. Even though there’s not really a boundary-scan function involved on the DDR4 side, this mode actually has been, as claimed by JEDEC, “designed to work seamlessly with any boundary-scan devices.” Here’s a brief introduction to what it does and how to test it with a boundary-scan (JTAG) tool.
Baseboard Management Controllers (BMCs) form the brains of any high-end Intel-based server platform: they perform system management functions ranging from fan speed control to remote user authentication. A new wave of these service processors is coming to market to support new capabilities needed on the next generation of Intel silicon. What are these unique features, and how will they be debugged?