More and
more chips uses onboard high-speed interconnect networks. Processors talking to
co-processors; data shuffling from fast memory access; complete chipset implementations
on 3rd party boards and so on. We consumers want action when we press a button,
right?!
Just one
problem. Built-in test techniques such as JTAG 1149.1 wasn’t built for
AC-coupled or differential high-speed signals. Something new was needed. And so
the extension to JTAG 1149.6 for Boundary-Scan Testing of Advanced Digital
Networks was born.
The new
standard specifies supplemental boundary-scan cells at advanced digital
networks and corresponding boundary-scan instructions to generate stimuli and
capture responses for AC coupling and/or differential signaling. Does it solve
all high-speed interconnect problems? Read more to find out.
This week Intel®
advanced embedded instrumentation a few steps – actually, a few leaps forward –
with its announcement of Intel® Silicon View Technology (Intel SVT). And
ScanWorks became the only tools platform to support all three pillars of Intel
SVT: platform debug, electrical validation and board manufacturing testing.
There are a few ICT testers that support one or two of the pillars, but not all
three, as ScanWorks does.
As we’ve covered in some previous blogs, the differential,
AC-coupled nature of PCI Express allows this bus to be somewhat self-healing,
whereby some structural defects will allow the bus to transparently run, albeit
at a degraded performance. Due to this, these short-circuit and open-circuit
defects may be completely masked from conventional functional test. But such
defects are important to detect, because they will affect the throughput of the
port. Boundary scan can be used to detect these defects, subject to the
implementation of IEEE 1149.1 and IEEE 1149.6 in the chips.
As boards come off the production line and appear dead in functional test, the going sure gets tough. Just a small problem in the wrong place and the board won’t boot. After that, you could have a nightmare of manual ‘hands-on’ work trying to revive it. Meanwhile, the boards keep coming off the production line and pretty soon there’s a growing pile of dead boards staring back at you. Not a pretty sight. And, of course, those production deadlines keep coming at you too.
Luckily, in almost all cases there is an onboard processor and a lot of them are from Intel®, which means they have a debug port. And that means BIST, JTAG, IJTAG and other embedded instrumentation technologies may be embedded in the board. The trick becomes how to combine them and put them to good use from a single test and debug environment that can provide answers fast. If not, the time you spend on dead board debug is probably not worth it.
Last month, we saw how defects on memory data lines can
cause a system to fail, and yet escape detection by the system boot loader or
BIOS. Let’s examine this in more technical detail.
Non-intrusive testing according to a
dictionary means: “testing that is transparent to the [software] under
test, i.e. does not change its timing or processing characteristics. Non-intrusive
testing usually involves additional hardware that collects timing or
processing information and processes
that information on other platforms”.
Non-intrusive board test. Does such a thing
really exist? If by the phrase you mean a test methodology that has no physical effect on the unit being
tested, then the answer is yes; it definitely exists. Non-intrusive board test
(NBT) uses soft access to onboard embedded instruments and test technologies like
BIST to test circuit boards. All it needs is a single point of connection – the
rest is software. Software to access, drive and collect data from test routines,
and then to make sense of it all for the user. Almost everything from the
processor out can be driven and tested without physical access to anything but
the processer itself. And the higher the speed, the more crucial this becomes.
Physically probing signals above 5 GHz is not a good thing.
Most engineers, present company included, probably
assumed at one time or another that the only way to validate the functionality
of system health monitors like those that operate on the I2C or SPI buses was
to develop and apply functional tests. Makes sense, right? Well, if you’re
interested in saving time, increasing your confidence in the functionality of
these devices and keeping your product development on schedule, the real answer
is: not really. Combining functional and structural test in one step early in
the prototype board bring-up process and then transferring the whole process to
manufacturing makes a lot more sense.
Last week we saw a $300,000 oscilloscope. This week, we look
at another one for $470,000. The sky’s the limit when it comes budgeting for
‘scopes. But aside from the price, what other advantages are there of embedded
instrumentation-based system marginality validation tools?
Think about it. Test without touching a single bus with probles. Test without expensive fixtures. Soft access through existing board connectors and JTAG ports to create virtual, re-programmable test points. Wherever you want them. Whenever you want them. Clearly, 'mechanical test' is the way of the past and a software-driven approach is the future. But it's here and now.
This is non-intrusive board test, or NBT, becuase it really does not contaminate your tests results in any physical way. And that is important as speed continues to increase and physical access goes away. Instead, non-intrusive test relies solely on a combination of embedded instrumentation, onboard test structures and tools that access the test object through software or 'soft access'.
Learn all about non-intrusive board test directly from Adam Ley, Chief Technologist at ASSET InterTech, provider of the soft access ScanWorks platform for board debug, validation and test, by registering for our eBook, "Defect Coverage | Non-intrusive Board Test eBook".
PXI is a hardware-based modular test standard. If PXI
users want to add test capabilities, they have to add another hardware module
to a PXI card cage. Now that’s changed with the new ScanWorks® PXI-1000
controller. Let’s say you have ScanWorks and a PXI-1000 controller and you’re
doing boundary-scan test (IEEE 1149.1 and 1149.6), but you want to detect a
broader spectrum of structural defects so you add another embedded
instrumentation test technology like IJTAG (IEEE P1687 Internal JTAG). No, you won’t
need another PXI-1000 controller. You just expand the capabilities of ScanWorks
and the PXI-1000 that’s already in your PXI chassis takes care of the rest. PXI,
meet embedded instrumentation.
More and
more chips uses onboard high-speed interconnect networks. Processors talking to
co-processors; data shuffling from fast memory access; complete chipset implementations
on 3rd party boards and so on. We consumers want action when we press a button,
right?!
