Test Data Out (TDO)

No Trouble Found?

In my earlier blog on Debugging Watchdog Timeouts I mentioned the dreaded No Trouble Found (NTF) problem. Some have asked why NTF is important. Well, the answer is because NTF is a huge cost to companies, compounded by the fact that NTF is extremely difficult to quantify and to address. Something as simple as an errant wedding ring can cost companies millions of dollars. Let me explain…

QPI Is Cool (Part II)

For those of us who are working with the new Intel® QuickPath Interconnect (QPI) high speed bus, there is a new book on the market that will enhance your understanding as well as become the “Bible” for high speed buses. The name of the book is “Mastering High Performance Multiprocessor Signaling” by Dave Coleman and Michael Mirmak. ASSET’s ScanWorks® tools were referenced as one of the validation measurement tools for gathering data on receiver margining specification. Here are the book details...

What is IEEE 1687?

Hello, and welcome—this is the first of a set of short blogs on the topic of 1687. Since 1687 is still in the proposal stage, it is actually referred to as P1687 right now, but the “P” will disappear after the standard is ratified and it is no longer a “proposal”. We are nearing the point where the committee is going to submit the draft of the standard for the ratification process, and there is a lot more interest being generated by early adopters, so there is a need for some explanation, understanding, and analysis concerning the costs, efficiencies, configurations and implementations of 1687 (also referred to as IJTAG, where the “I” means “internal”). This first blog answers the question, “what is IEEE 1687”, and subsequent blogs will cover the topics “who uses IEEE 1687”, “what are the advantages of using IEEE 1687 (why use IEEE 1687)”, and “how to use IEEE 1687.”

Debugging watchdog timeouts

Watchdog timeouts occur in crashed or hung systems when the main processor on a printed circuit board no longer sends a heartbeat to an ancillary service processor. The service processor watchdog then, after the timeout period, re-initializes the main system to try to restore it to an operational state. Watchdog timeouts can occur in high- and low-end systems, anywhere from routers to servers to cell phones. Debugging these can be difficult…

Intel® Xeon® Processor 7500 Series (codenamed Nehalem-EX)

The new Intel® Xeon® Processor 7500 Series (codenamed Nehalem-EX) is truly a leap forward for Intel server technology and forms the foundation for high-end clusters and supercomputers for years to come. Capable of scaling up to 256 processors and supporting 16 terabytes of memory, it will be used in high-performance “super nodes” running bandwidth-demanding applications like financial analysis, numerical weather predictions and genome sequencing. In short, this Intel platform rocks. The diagram below shows the new architecture, which is explained in our free whitepaper...

iNEMI Built-In Self-Test Project Wrap-Up

Last week iNEMI (the International Electronics Manufacturing Initiative) concluded its nine-month project investigating Built-In Self-Test (BIST). The purpose of the iNEMI Project was to develop and promote the adoption of chip BIST at the board and system level. ASSET staffers participated in the Project, as part of our embedded instrumentation initiative and our drive to standardize IC BIST using technologies such as IEEE P1687 (IJTAG). Here's a summary of the conclusions...

Why do I have to validate my board design?

For some of us this is a rhetorical question. Of course you will need to validate!! However, I’m surprised how much I am seeing this mindset in the marketplace.

ASSET has been providing validation tools for Intel Architecture (IA) based designs for the last six years. During this time, we have seen a significant increase in signal speeds that has created challenges to the signal integrity (SI) engineer. For example, moving to the Intel® QuickPath Interconnect (Intel QPI) bus changed the validation process. The maximum Intel QPI frequency on Nehalem is 3.2 GHz (6.4 GT/s). To put this in perspective, the maximum Front Side Bus frequency was 200 MHz. In one generation of IA based products, there was a 16x speed increase!

This increase in speed requires a new approach from designers. Read on...

QPI Is Cool...

Many of us are responsible for validating and testing Intel®-based designs. The latest Intel® Xeon® and Itanium® processor platforms use Intel’s QuickPath Interconnect (QPI) to tie the processor and the I/O hubs together into single, dual, and multi-processor systems. ASSET got a nice promotion in Intel’s book on QPI: “Weaving High Performance Multiprocessor Fabric: Architectural Insights into the Intel QuickPath Interconnect”.

For those who might be interested in the book, it’s available for about $80 from www.amazon.com. On pages 257-259, Intel talks about the ASSET ScanWorks® IBIST (Interconnect Built-In Self Test) tool. To quote:

Test Pads on High-Speed Nets

Recently I read a posting from a well-known In-circuit Test (ICT) vendor defending the use of test pads on high-speed signals. I found this message to be rather amusing, since the prevailing wisdom is to avoid these to prevent signal integrity issues.

The posting went something like this:

We have done some simulations that indicate that test pads can still be used for high speed signals if they are properly designed and added correctly to the PCB. The test pad must be on the signal etch without a stub connecting the etch to the pad. Also, there should not be a via connecting the etch to the test pad.

The results indicate that a 35 mil pad on a 5 mil wide etch is OK for 10Gb/s with 30ps rise/fall times.

If there is still a worry about test pads, the test pad can always be "compensated" by removing some of the reference plane below the test pad to diminish the additional capacitance that might otherwise occur. If the test pad per-unit capacitance and inductance is nearly equal to the per unit capacitance and inductance of the transmission line's etch, then the test pad will have no net negative effect to the signal transmission.

The first paragraph correctly highlights some of the pitfalls of putting test pads on high-speed signals. The trend these days is to route traces for high-speed signals on inner layers of the PCB – in which case it is only possible to add a test pad by way of a via, which is not a good idea.

Ever heard of PCOLA/SOQ/FAM ?

I’ve been in the test engineering industry for over a decade and the concept of test coverage has always been of great interest to me. How do test engineers quantify the amount of test coverage they get on a particular board design? We know from experience that every design is different and, therefore, every design needs a slightly different test strategy. That’s what makes our jobs as test engineers ever-changing and fresh. We’re always learning about new test strategies, technologies and methodologies and applying them to the task at hand. So as boards get bigger, denser, faster and more complex, we apply our creativity to keep test coverage apace with the changes.

Sometimes I wonder, is this science or black magic? I believe it’s both. One scientific innovation I’ve seen recently is the adoption of PCOLA/SOQ/FAM by iNEMI. Yeah, I know that’s a lot of letters strung together, but here’s what it means. iNEMI is the International Electronics Manufacturing Initiative and it is spearheading an industry effort to scientifically characterize test coverage. And that’s what PCOLA/SOQ/FAM is. Here’s what the alphabet soup means: