Test Data Out (TDO)

Why you need boundary scan in your board bring-up toolset

Did you ever need a new board coming off the production line yesterday and it wouldn’t boot? It didn’t even try to come up and gave you no hint why?  Typically you’d connect a debugger tool to see if you could get some signs of life. You might put some code into memory to start running some tests. But there’s no response from the processor and you can’t access any of the memory parts on the board. You’re stuck...

Performance versus Conformance Testing

OEMs in the telecom industry invest in verifying the performance and conformance of the high-speed interconnects off their gear. Does the same approach apply to chip-to-chip interconnects, and in other industries?

Your laptop - are you getting what you paid for?

Many of us got new laptops, e-readers, tablets, and other electronics toys as gifts over the holidays. But do these machines run as fast as they’re supposed to?

The Coming Crisis in Board Bring-Up

I was reflecting on how much processor speeds, memory, and data transmission rates have increased over the last few decades. And yet the same old tools and techniques are often used to bring up new designs. When do you think we fall off the cliff?

Programming devices at In-Circuit Test?

I read a very interesting article recently making the case for programming PLDs and Flash Memory at In-Circuit Test (ICT). What do you think?

Debugging CATERR and other failures

The challenge of system debug on Intel (and other) systems can be huge. What new tricks are available for debugging system hangs, crashes, or application errors?

Don't be Intrusive!

Ever heard the old saw about the guy (gal) that “went to a fight and a hockey game broke out”?

I’d characterize the ongoing debate on the value and longevity of In-Circuit Test (ICT) as a bit of a brawl…

Solving Intel QuickPath Interconnect and DDR Margining Issues

This past week ASSET and Intel did a presentation at the Intel Developers Forum (IDF) on using ScanWorks to solve QPI and DDR3 margining problems.

What is P1838 3D test?

Although it has been in the news for quite a while, one of the methods thought to be the way to extend Moore’s Law is finally reaching the point where it may be deployed in the near future — 3D Silicon Integration…

P1838: the 3D Standard and its use with 1687

One of the newest IEEE Standards Committees is currently defining the P1838 3D Test Standard. The main goal of P1838 is to develop a “Per Die” Access Mechanism that becomes a “Stacked Die” Access Mechanism when the individual die are stacked into 3D silicon. The main focus is to handle the configuration of stacking die that are connected to each other using Through-Silicon-Vias (TSV’s) to make 3D silicon integration, which is different from Package-on-Package and other 3D packaging techniques. Find out more…