Test Data Out

Defects on High-Speed Memory – Part 2

Last month, we saw how defects on memory data lines can cause a system to fail, and yet escape detection by the system boot loader or BIOS. Let’s examine this in more technical detail.

High-Speed Non-Intrusive Board Test | PCI, QPI

Non-intrusive testing according to a dictionary means: “testing that is transparent to the [software] under test, i.e. does not change its timing or processing characteristics. Non-intrusive testing usually involves additional hardware that collects timing or processing  information and processes that information on other platforms”.

Non-intrusive board test. Does such a thing really exist? If by the phrase you mean a test methodology that has no physical effect on the unit being tested, then the answer is yes; it definitely exists.  Non-intrusive board test (NBT) uses soft access to onboard embedded instruments and test technologies like BIST to test circuit boards. All it needs is a single point of connection – the rest is software. Software to access, drive and collect data from test routines, and then to make sense of it all for the user. Almost everything from the processor out can be driven and tested without physical access to anything but the processer itself. And the higher the speed, the more crucial this becomes. Physically probing signals above 5 GHz is not a good thing.

Functional testing of I2C and SPI system monitors with JTAG

Most engineers, present company included, probably assumed at one time or another that the only way to validate the functionality of system health monitors like those that operate on the I2C or SPI buses was to develop and apply functional tests. Makes sense, right? Well, if you’re interested in saving time, increasing your confidence in the functionality of these devices and keeping your product development on schedule, the real answer is: not really. Combining functional and structural test in one step early in the prototype board bring-up process and then transferring the whole process to manufacturing makes a lot more sense.

Here’s why.

SIV versus SMV – Part 2

Last week we saw a $300,000 oscilloscope. This week, we look at another one for $470,000. The sky’s the limit when it comes budgeting for ‘scopes. But aside from the price, what other advantages are there of embedded instrumentation-based system marginality validation tools?

Defect Coverage | Non-intrusive Board Test eBook

Think about it. Test without touching a single bus with probles. Test without expensive fixtures. Soft access through existing board connectors and JTAG ports to create virtual, re-programmable test points. Wherever you want them. Whenever you want them. Clearly, 'mechanical test' is the way of the past and a software-driven approach is the future. But it's here and now. 

This is non-intrusive board test, or NBT, becuase it really does not contaminate your tests results in any physical way. And that is important as speed continues to increase and physical access goes away. Instead, non-intrusive test relies solely on a combination of embedded instrumentation, onboard test structures and tools that access the test object through software or 'soft access'.

Learn all about non-intrusive board test directly from Adam Ley, Chief Technologist at ASSET InterTech, provider of the soft access ScanWorks platform for board debug, validation and test, by registering for our eBook, "Defect Coverage | Non-intrusive Board Test eBook".

PXI meets embedded instrumentation

PXI is a hardware-based modular test standard. If PXI users want to add test capabilities, they have to add another hardware module to a PXI card cage. Now that’s changed with the new ScanWorks® PXI-1000 controller. Let’s say you have ScanWorks and a PXI-1000 controller and you’re doing boundary-scan test (IEEE 1149.1 and 1149.6), but you want to detect a broader spectrum of structural defects so you add another embedded instrumentation test technology like IJTAG (IEEE P1687 Internal JTAG). No, you won’t need another PXI-1000 controller. You just expand the capabilities of ScanWorks and the PXI-1000 that’s already in your PXI chassis takes care of the rest. PXI, meet embedded instrumentation.

Signal Integrity Validation (SIV) versus System Marginality Validation (SMV)

Back a few years ago, engineers used expensive high-end oscilloscopes to perform signal integrity validation (SIV) on their designs, and considered that adequate in determining the success of a design. But with today’s products, process and parameter variations occur that require system marginality validation (SMV) to be done by less expensive software-based tools, to determine if a design is ready for high volume production.

Defects on High-Speed Memory

In previous blogs we covered the kind of defects that might exist on high-speed serial I/O and their associated impacts on system performance and stability. A similar analysis on DDR SDRAM yields some interesting findings.

SVF | Serial Vector Format Specification | JTAG | Boundary Scan

Serial Vector Format (SVF) files are used to describe high-level IEEE 1149.1 bus operations. The format was defined long ago by Texas Instruments and Teradyne, but it is still considered the de facto standard for passing serial vectors between tools used in design and test of chips and circuit boards.

Today, the specification is maintained by ASSET InterTech, Inc., a spin-off of Texas Instruments. To be certain you have the latest version of the document, go to the source.  ASSET has set up a web page that will always point to the current version of the SVF document.  To get the SVF specification, click on the link below.

SVF | Serial Vector Format Specification JTAG Boundary Scan | eBook 

 

 

Structural Defects on High-Speed Serial I/O - Part 3

In the first two parts of this multi-part blog, we reviewed different kinds of short circuit, open circuit, and stuck-at faults and how they might affect link performance. Let’s recap and rank these defects and see what we can do about them.